EDN

SRAM stability at 45 nm: is dynamic bias adjustment an answer?

As SRAM geometries continue to shrink, some of the design problems get more and more pressing. One of these is the matter of read and write margins. Roughly, read margin measures the stability of the ...
Business Wire

Renesas Electronics Develops Two-Port On-Chip SRAM Specialized in Improving Video Processing Performance of Vehicles for the Autonomous-Driving Era

Now, with practical usability in mind, Renesas has developed a double-pumping circuit technology using single-port SRAM cells that allows independent read and write operations, to realize reduced ...
Design-Reuse

Low Power 7T SRAM Cell Scheme - ''Saving Write Zero Power''

This paper presents a Seven-transistor SRAM cell intended for the advanced microprocessor. A low power write scheme, which reduces SRAM power by using seven-transistor sense-amplifying memory cell, ...
Design-Reuse

How To Interface DDR-II SRAMs with Stratix II Devices

DDR-II SRAM devices offer enhanced timing margin and flexibility. This article is a step-by-step guide to interfacing DDR-II SRAMs with Stratix II devices for high-bandwidth communications, networking ...
Semiconductor Engineering

SRAM With Mixed Signal Logic With Noise Immunity in 3nm Nanosheet (IBM)

A new technical paper titled “SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology” was published by researchers at IBM T. J. Watson Research Center and IBM. “A modular 4.26Mb ...