HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design ...

As total system complexity grows, so does verification complexity. To speed simulation time and improve functional coverage of the RTL ASIC under test, the transactors used for RTL verification must ...

This paper shows a way to connect a FPGA based prototyping environment with a HDL simulator. When the pure cosimulation feature is used, speedups in a range from 2 to 50 are achievable. We show a new ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...

San Mateo, Calif. – As the size of the verification problem in system-on-chip design has become apparent, design teams have been throwing any resources they can lay their hands on at the problem.

Its use results in faster development, cleaner testbenches, and a modern software-oriented approach to validating FPGA and ASIC designs without replacing your existing simulator.

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...

Doubling the performance of the previous release, Version 6.2 of Active-HDL is an integrated, Windows-based HDL design and simulation environment. Behavioral, gate-level, and timing simulation ...

Free software licenses and operating systems like GNU/Linux make it possible to learn programming and customize state-of-the-art software in countless ways. Hacking software, however, isn't the last ...

Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And ...

Henderson, USA – December 3, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...