Semiconductor Engineering

PF-DRAM: A Precharge-Free DRAM Structure

“Although DRAM capacity and bandwidth have increased sharply by the advances in technology and standards, its latency and energy per access have remained almost constant in recent generations. The ...
조선일보

Samsung Electronics develops dual DRAM strategy with 9nm vertical and planar structures

Samsung Electronics aims to commercialize 9nm (nanometer, 1 billionth of a meter) DRAM within three years and plans to introduce the '4F²' DRAM structure, which changes the structure from horizontal ...
Semiconductor Engineering

Uncovering The Size, Structure, And Operation Of DRAM Subarrays And Showing Experimental Results Supporting The Cause Of Rowhammer

We first uncover the size, structure, and operation of DRAM subarrays and verify our findings on the characteristics of DRAM. Then, we correct misunderstood information related to AIBs and demonstrate ...
EDN

Toshiba’s DRAM cell piggybacks on SOI wafer

Tokyo – Toshiba Corp. has developed a new cell structure for embedded DRAM on silicon-on-insulator wafers that takes advantage of SOI's specific characteristics. The cell will be an essential ...
조선일보

Samsung and SK hynix rapidly develop 4F² DRAM to transition to 3D technology

Samsung Electronics and SK hynix are accelerating their research and development (R&D) of three-dimensional (3D) DRAM, and they are reported to plan to develop and initiate verification work on the ...
TweakTown

SK hynix unveils DRAM memory chip roadmap for the next 30 years: 4F2VG tech, 3D DRAM, and more

TL;DR: SK hynix unveiled a 30-year DRAM roadmap featuring 4F2 Vertical Gate and 3D DRAM technologies to enhance performance, integration, and power efficiency beyond 10nm scales. These innovations aim ...
EDN

Toshiba, Sony take trench capacitors to 90-nm node

TOKYO — Toshiba Corp. said it is leveraging its deep-trench-capacitor DRAM structure, which it has championed as a process driver since the 0.25-micron generation, to migrate its system-on-chip ...
ExtremeTech

Forget Moore's law: Hot and slow DRAM is a major roadblock to exascale and beyond

Any attempt to truly push the future of computing means fundamentally redesigning memory -- but after 40 years, can DRAM be easily swept aside? Share on Facebook (opens in a new window) Share on X ...
Design-Reuse

Renesas Electronics Announces Development of the Basic Structure for Embedded DRAM with High Compatibility with Standard CMOS Logic Circuits

TOKYO, Japan, December 9, 2010 — Renesas Electronics Corporation (TSE: 6723), a premier provider of advanced semiconductor solutions, today announced the development of a basic structure for ...
Embedded

Happy birthday DRAM!

On June 4, 1968, Robert Dennard was granted a patent for a single transistor, single capacitor DRAM cell design idea. This doesn’t sound earth-shattering today, but back in the sixties, this was a ...
ExtremeTech

Forget Moore's law: Hot and slow DRAM is a major roadblock to exascale and beyond

Any attempt to truly push the future of computing means fundamentally redesigning memory -- but after 40 years, can DRAM be easily swept aside? Share on Facebook (opens in a new window) Share on X ...